An Asynchronous Scan Path Concept for Micropipelines using the Bundled Data Convention

Abstract: macros that can be embedded into synchronous circuitry was This paper presents a Scan path design to ease the controllability presented in [89LeenS]. To test the asynchronous modules a and observability of Self-timed logic. The Scan path registers synchronous scan test is presented there. In contradiction, the operate in asynchronous mode during operation and test. asynchronous machine operates under speed-independent Therefore, no synchronous test clock is necessary during the test conditions in non-test mode. In [91GuilSY] and [93SaloK] a standard mode. New test control modules provide the control sequences to cell design for testable Self-timed systems was presented with a switch between the parallel data path and the serial Scan path. In clock based synchronous Scan path using non overlapping clock addition to the data path, the control path and the bundled data cycles like LSSD. interface is integrated into the test concept. The new Scan path VLSI synthesis tools for asynchronous circuits usually create a register has been developed with low area overhead and a small design derived from a high-level language. To enhance the additional delay in the critical data path. An example is used to testability of these asynchronous circuits the formal language is verify this DFT modules for the data and the control path. It increased by new modules. A compiler integrates the modules into demonstrates the functionality during test and operational mode a standard circuit representation [93LavaS]. A test concept for a and the compact realization of the asynchronous scan register. VLSI synthesis tool of asynchronous design, named Tangram, was